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E2F0004-27-X1
Semiconductor MSM7660
Semiconductor Digital Video Decoder (NTSC/PAL Compatible)
This version: Jan. 1998 MSM7660 Previous version: Oct. 1997
GENERAL DESCRIPTION
The MSM7660 is a decoder which converts digitally sampled NTSC or PAL video signals to the format based on ITU-RBT601. The MSM7660 can accept composite video and S video signals. For composite signals, the MSM7660 converts signals to YUV data via a 2-dimensional Y/C separation circuit. For S video signals, the MSM7660 converts signals to YUV data by passing the 2-dimensional Y/C separation circuit. An internal AGC/ACC circuit makes decoding of images relatively easy. Video signals are internally synchronized, so a relatively wide range of video signals can be decoded without using an external VCO circuit.
FEATURES
* Accepts composite video and S video signals * Compatible with NTSC/PAL * 2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S video signal input) NTSC: 3 lines/2 lines PAL: 2 lines * Sampling frequency 14.75 MHz (PAL Square Pixel) 14.31818 MHz (NTSC 4Fsc) 12.27 MHz (NTSC Square Pixel) 13.5 MHz (ITU-RS601) * Internal AGC/ACC circuit * 8-bit Y/C (CbCr) output (conforms to ITU-RBT601) YCbCr: 4:2:2 YCbCr: 4:1:1 * High impedance output possible, priority cascade control function * I2C-BUS interface * External terminal mode (default) or internal register mode can be selected for operation mode setting. * A frequency one or two times the sampling clock is supplied to LSI * Power consumption: 500 mW (Typ. 13.5 MHz) * Package: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM7660GS-BK)
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BLOCK DIAGRAM
Semiconductor
CLKX2 CLKX2O CLKO
CLKDIV HDET HCL HSY
CS_L
VS_L
VVALID ODD OE_L
HS_L
HVALID
X X_L
Synchronization Block
Y[7:0]
CVBS[7:0]
lum. Prologue Block
Luminance Block (AGC+BPF)
Epilogue Block
(2Dim. Y/C separate) CD[7:0] Line Memory (1Kb) 2 chr. Chrominance Block (ACC+LPF)
MODE[3:0] C[7:0] IIC-bus Control Logic Test Control Logic Output Formatter
SCL
SDA
RESET_L
TE TI
TO
TEST1
TEST0
COEI
COEO
MSM7660
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Semiconductor
MSM7660
PIN CONFIGURATION (TOP VIEW)
70 CSYNC_L 69 HSYNC_L 68 VSYNC_L 67 HVALID
80 CLKX2 79 CLKX2O
78 CLKO 77 CLKDIV
X1 X_L 2 VDD3 3 GND 4 CD[0] 5 CD[1] 6 CD[2] 7 CD[3] 8 CD[4] 9 CD[5] 10 CD[6] 11 CD[7] 12 VDD5 13 GND 14 CVBS[0] 15 CVBS[1] 16 CVBS[2] 17 CVBS[3] 18 CVBS[4] 19 CVBS[5] 20 CVBS[6] 21 CVBS[7] 22 VDD3 23 GND 24
66 VVALID 65 ODD
64 TEST1 63 TEST0 62 VDD3 61 GND 60 C[0] 59 C[1] 58 C[2] 57 C[3] 56 C[4] 55 C[5] 54 C[6] 53 C[7] 52 VDD5 51 GND 50 Y[0] 49 Y[1] 48 Y[2] 47 Y[3] 46 Y[4] 45 Y[5] 44 Y[6] 43 Y[7] 42 VDD3 41 GND
74 VDD5 73 HDET
76 GND 75 VDD3
VDD5 25 VDD3 26
GND 27 SCL 28
SDA 29 MODE[0] 30 MODE[1] 31
MODE[2] 32 MODE[3] 33
RESET_L 34 TE 35
72 HCL 71 HSY
TI 36 TO 37 COEI 38
80-Pin Plastic QFP
COEO 39 OE_L 40
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Semiconductor
MSM7660
PIN DESCRIPTIONS
Pin 1 2 3 4 5 to 12 13 14 15 to 22 23 24 25 26 27 28 29 30 to 33 Symbol X X_L VDD3 GND CD[0 to 7] VDD5 GND CVBS[0 to 7] VDD3 GND VDD5 VDD3 GND SCL SDA MODE[0 to 3] I I/O I I2C-bus clock pin I2C-bus data pin Mode input pins. Dip switches can be used because these pins are internally pulled-up. MODE[3] MODE[2:0] 0: composite 1: S video 000: NTSC 001: NTSC 010: NTSC 100: PAL 101: PAL others: 34 35 36 37 38 39 40 41 42 RESET_L TE TI TO COEI COEO OE_L GND VDD3 Internal logic power supply (3.3 V typ.) I I I O I O I ITU-RS601 Square Pixel 4Fsc ITU-RS601 Square Pixel Undefined 13.5MHz 12.27 MHz 14.32 MHz 13.5 MHz 14.75 MH Peripheral I/O power supply (5 V typ.) Internal logic power supply (3.3 V typ.) I Composite digital data input pin Luminance signal is input for S video input. Internal logic power supply (3.3 V typ.) I Chrominance signal input pin (valid only for S video input) Set to "L" level at composite signal input Peripheral I/O power supply (5 V typ.) I/O I O Test pin. Normally, to "L" level. Unused pin. Internal logic power supply (3.3 V typ.) Description
System reset input pin (active at "L") Test pin. Normally, set to "L" level Test pin. Normally, set to "L" level Test pin Cascade priority control input pin Connected to COEO of decoder with higher priority. Cascade priority control output pin Outputs "L" when COEI is "L" or when this LSI is in output enable status. Y/C/HSYNC-L/VSYNC-L output enable input pin (active at "L") OR condition with register setting
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Semiconductor
MSM7660
Pin 43 to 50 51 52 53 to 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol Y[7 to 0] GND VDD5 C[7 to 0] GND VDD3 TEST0 TEST1 ODD VVALID HVALID VSYNC_L HSYNC_L CSYNC_L HSY HCL HDET VDD5 VDD3 GND CLKDIV CLKO CLKX2O CLKX2
I/O O Luminance signal output pin
Description
Peripheral I/O power supply (5.0 V typ.) O Chrominance signal output pin Internal logic power supply (3.3 V typ.) I I O O O O O O O O O Input pin for testing. Normally use this pin at open state or "H" level. Input pin for testing. Normally use this pin at open state or "H" level. Field display output pin Outputs "H" for odd field. Vertical valid line timing output pin Horizontal valid pixel timing output pin V sync output pin H sync output pin Composite sync output pin Sync chip timing output pin for AD converter Clamp timing output pin for AD converter HLOCK synchronization detection display output pin (Outputs "H" when H synchronization is established.) Peripheral I/O power supply (5.0 V typ.) Internal logic power supply (3.3 V typ.) I O O I Clock select input pin Inputs "H" when a half CLKX2 is used as the internal clock. Clock output pin Outputs internal clock. Clock output pin Bypasses clock input and outputs clock input. Clock input pin (a clock one or two times the sampling clock is input)
[Clock supply method and handling] 1.Supplying double pixel clock from external supply source
CLKDIV
2.Supplying pixel clock from external supply source
CLKDIV
CLKX2
X
XL
Clock supply source
CLKX2
X
XL
Clock supply source
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Power Consumption Storage Temperature Symbol VDD5 VDD3 VI PW TSTG Condition Ta=25C Ta=25C Ta=25C -- -- Rating -0.3 to +7 -0.3 to +4.5 -0.3 to VDD5 +0.3 800 -55 to +150 Unit V V mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Power Supply Voltage High Level Input Voltage High Level Input Voltage Low Level Input Voltage Operating Temperature Range Symbol VDD5 VDD3 GND VIH1 VIH2 (*1) VIL Ta Condition Ta=25C Ta=25C Ta=25C -- -- -- -- Min. 4.5 3.0 -- 2.2 0.8VDD5 0.0 0 Typ. 5.0 3.3 0.0 -- -- -- -- Max. 5.5 3.6 -- VDD5 VDD5 0.8 70 Unit V V V V V C
*1:
CCKX2, CLKDIV, SDA
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=0 to 70C, VDD3=3.3V0.3V, VDD5=5V10%) Parameter High Level Output Voltage Symbol VOH Condition IOH=-2mA (*1) IOH=-4mA (*2) IOH=-8mA (*3) IOL=2mA (*1) Low Level Output Voltage VOL IOL=4mA (*2) IOL=8mA (*3) VI=GND to VDD5 Input Leak Current Output Leak Current II IO VI=GND to VDD5 PULL-UP=50k (*4) VI=GND to VDD5 3V system Power Supply Current (operating) IDD
CLK=15MHz
Min. 0.8VDD5
Typ. --
Max. VDD5
Unit V
0 -10 -250 -10 -- -- -- -- 0 3
-- -- -- -- 110 20 1 50 -- --
0.8 10 -20 10 150 30 3 200 0.4
V
mA mA mA mA mA mA V mA
5V system
Power Supply Current (standby) SDA Output Voltage SDA Output Current
IDDS SDAVL SDAIO
3V system 5V system -- --
*1: *2: *3: *4:
TO HSYNC_L, VSYNC_L, HDET, COEO Y[7:0], C[7:0], HCL, HSY, HSY, CSYNC_L, HVALID, VVALID, ODD, CLKX2O, CLKO MODE[3:0], COEI, TEST0, TEST1
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Semiconductor AC Characteristics
MSM7660
(Ta=0 to 70C, VDD3=3.3V0.3V, VDD5=5V0.5V) Parameter Symbol Condition PAL Square Pixel CLKX2 cycle time tCLKX2 NTSC 4Fsc NTSC Square Pixel ITU-RS601 Input Data Setup Time Input Data Hold TIme Output Data Delay Time* Output Data Set Time* Output Data Disable Time*
Cascade Priority Signal Delay Time*
Min. -- -- -- -- 20 0 5 2 2 2 5 6 8 200 -- 100
Typ. Max. 33.9 34.9 40.75 37.05 -- -- -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- -- 30 12 13 14 14 20 22 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns MHz % ns
tIS tIH tOD tODS tODD tCPD tCXD tCD1 tCD2 tC_SCL tD_SCL tL_SCL
-- -- -- -- -- -- -- -- -- Rpull_up=4.7kW -- Rpull_up=4.7kW
Output Clock Delay Time*
Output Clock Delay Time* (CLKDIV: Low) (Internal clock) (CLKDIV: High)
Clock Cycle Time Clock Duty Cycle Low level Cycle
(*output load 15pF)
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Semiconductor Input and Output Timing
MSM7660
CLKX2
CLKX2O
CLKO
CVBS CD HCL, HSY CSYNC_L HVALID, VVALID ODD, HDET Y,C HSYNC_L VSYNC_L OE_L COEI
,,
CLKDIV : Low tCXD tCD1 tIS tIH not valid not valid tOD HI-Z tODS tODD tCPD tCPD
CLKDIV : High
tCXD
tCD2
COEO
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Semiconductor
MSM7660
BLOCK DESCRIPTION
1. Prologue Block
The prologue Block performs Y/C separation using a 2-dimentional adaptive comb filter when composite signals (CVBS) are input. The following operation modes can be changed via the I2C-bus. The * mark indacates a default. The default is a state that is selected when reset. 1) Video input mode select Composite video input * S video input 2) Video input mode select NTSC system* PAL system 3) Operation mode select NTSC ITU recommendation BT.601 MTSC Square Pixel NTSC 4Fsc PAL ITU recommendation BT.601 PAL Square Pixel 4) Y/C separation mode select Adaptive comb filter is used. * Unadaptive comb filter is used. Comb filter is not used. The adaptive comb filter detects the correlation up to 3 lines between continuous lines. The Y/ C is separated by the comb filter according to the way of correlation if theses lines are correlated. The Y/C is separated by the trap filter if these lines are not correlated not correlated (only 2 lines in the case of PAL). In the unadaptive comb filter, the Y/C is always separated by removing the luminance component based on the average of preceding and following lines (when there is the correlation between 3 lines). If the comb filter is not used, the Y/C is separated by the trap filter. The Y/C separation circuit is bypassed by S video signal input. In adittion, the functions of this block work only when lines are valid as image information. The processing of CVBS signals is not made during V-blanking. 2. Luminance Block
13.5MHz* 12.27MHz 14.32 MHz 13.5MHz 14.75 MHz
The luminance block removes synchronous signals from the signals containing luminance components after Y/C separation. The signals are corrected and output as luminance signals. This block can select the follwing operation modes. 1) Use of prefilter and sharp filter Used* Not used These filters are used for enhancing the edges of luminance component signals. 10/35
Semiconductor 2) AGC loop filter time constant select slow medium fast fixed
MSM7660
Factor value 1/1024n 1/64n* 1/n 0
3) Parameter for AGC reference level fine adjustment 4) Parameter for sync separation level fine adjustment The luminance signals are synchronized by AGC correction values obtained by the above processings 5) Selection of aperture bandpass filter coefficient middle range* high range 6) Coring range select off* 4LBS 5LBS 7LBS 7) Aperture weighting factor select 0* 0.25 0.75 1.5 The profile of these signals can be corrected by coring and aperture correction. 8) Use of pixel position correction circuit Used* Not used 3. Chrominance Block
This is a chroma signal processing block. The following modes can be selected. 1) Use of color bandpass filter Used* Not used 2) AGC loop filter time constant select slow medium fast fixed
Factor value 1/1024n 1/64n* 1/n 0
3) Parameter for burst level fine adjustment
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4) The threshold level for valid chroma amplitude is selected base on a color burst ratio. 0.5 0.25* 0.125 5) Color killer mode select Auto color killer mode* Forcible color killer 6) Parameter for color subcarrier phase fine adjustment In this block, chroma signals pass through the chroma bandpass filter to cut an unnecessary band. To maintain a constant chroma level, UV demodulation is performed on these signals via the ACC correction circuit. (this filter can be bypassed.) If the demodulation result does not reach a specified level, color killer signals are generated to fix the ACC gain. This functions as an auto color killer control circuit. The UV demodulation result is output as chrominance signals via a low pass filter. 4. Synchronization Block
This is a synchronizing signal processing block. Chip output synchronizing signals and synchronizing signals for internal use are generated by this block. Various signals are output in this block and the following operation modes can be selected. 1-1) Fine adjustment of HSY signal (start side) 1-2) Fine adjustment of HSY signal (stop side) 2-1) Fine adjustment of HCL signal (start side) 2-2) Fine adjustment of HCL signal (stop side) 3) HSY, HCL signal enable select High Level* Active These signal are used to sink chip and clamp timing to the A/D converter 4) Fine adjustment of HSYNC_L signal 5-1) Fine adjustment of HVALID signal (start side) 5-2) Fine adjustment of HVALID signal (stop side) 6-1) Fine adjustment of VVALID signal (start side) 6-2) Fine adjustment of VVALID signal (stop side) The data signals are transmitted or received at the rising edge of the HVALID signal. 7) TV, VTR mode select TV mode VTR mode* The TV mode or VTR mode in synchronizing mode is selected. The TV mode outputs a fixed pixel number per one line. The VTR mode outputs the results of decoding in accordance with the HSYNC signal regardless 12/35
Semiconductor of whether a jitter exists or not. Some VTR may disturb synchronization. 5. Epilogue Block
MSM7660
The Epilogue Block outputs UV signals from the chrominance block and Y signals from the luminance block in the format based on the signal obtained by setting of the control register. In this block, the following modes can be selected. 1) Display of blue back when synchronization fails. OFF ON* 2) Output signal Y/CbCr format select YCbCr 4:1:1 YCbCr 4 : 2 : 2* The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an output format described later. 3) Selection of 8-bit chroma signal output format Offset binary* 2's Complement 4) Output pin enable select High impedance Output enable* The Epilogue Block has a high impedance priority cascade control function to enable the bus connection of output signals. The target tristate buses are Y, C, HSYNC_L and VSYNC_L, and this block makes an output enable instruction for these signals 5) Luminance signal phase adjustment normal* forward 1 clock backward 1 clock 6) Chrominance signal phase adjustment normal* forward 1 clock backward 1 clock 6. I2C Control Block
This is the serial interface block based on the I2C standard of Phillips Corporation. This block functions only as a Slave-Receiver. The external control can set the internal registers (MRA, MRB, HSYT, etc.). 7. Test Control Block
This block is used to test this LSI. Normally it is not used.
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FUNCTIONAL DESCRIPTION
Input Signal Level Input signal is 8-bit in a straight binary format. The recommended input range is shown below.
255 reserved 232 Iuminance 128 chrominance +DC
60 sync 0
Input black level 56
CVBS[7:0] input range
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Semiconductor Output format The YCbCr 4:2:2 format and 4:1:1 format are shown below. The output format can be changed by register settings.
OUTPUT Y7(MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0(LSB) C7(MSB) C6 C5 C4 C3 C2 C1 C0(LSB) Y point C point PIXEL BYTE SEQUENCE Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 0 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 2 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 4 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 5 OUTPUT Y7(MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0(LSB) C7(MSB) C6 C5 C4 C3 C2 C1 C0(LSB) Y point C point Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 0
MSM7660
PIXEL BYTE SEQUENCE Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 1 0 YCbCr 4:1:1 format Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 5 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 6 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 7
YCbCr 4:2:2 format
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Semiconductor Timing Description AD Converter Support Signal
MSM7660
The timing wave form of HSY/HCL signals, which measure the sync chip and clamp timing for the AD converter, is as follows.
CVBS
COLOR BURST
HSY HCL
Horizontal sync Indication HSY and clamping HCL
Line control signal The line control signal timing is as follows.
CLK CLKO HVALID Y[7:0] C[7:0] Y0 Cb0 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y(n) Cb(n) Y(n+1) Cr(n)
Line Control Timing
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Semiconductor Vertical Synchronizing 4.3 Signal The vertical synchronizing signal timing is as follows.
524 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD 262 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD 263 264 265 266 267 268 269 270 271 272 273 274 525 1 2 3 4 5 6 7 8 9 10 11
MSM7660
12
275
Vertical Timing (NTSC: 60Hz)
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Semiconductor
MSM7660
621 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD 309 CVBS HVALID HSYNC_L CSYNC_L VSYNC_L VVALID ODD
622
623
624
625
1
2
3
4
5
6
7
8
9
310
311
312
313
314
315
316
317
318
319
320
321
322
Vertical Timing (PAL: 50Hz)
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Semiconductor Horizontal Synchronizing Signal The horizontal synchronizing signal timing is as follows.
MSM7660
Y[7:0]
HVALID HSYNC_L 60pixel
Horizontal Timing I2C-bus Interface Input/Output Timing The basic input/output timing of the I2C-bus interface is as follows.
SDA SCL
MSB
S Start Condition
1
2
7
8
9 ACK
1 tC_SCL
2 3-8
9 ACK
P Stop Condition
Data Line Stable: Data Valid Change of Data Allowed
I2C-bus Basic Input/Output Timing
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I2C BUS FORMAT
The I2C-bus interface input format is shown below.
1 cycle S Slave Address A S Symbol S Slave Address A Subaddress Data n P Start condition Slave address 1000001, 8th bit is write signal. Acknowledge. Generated by slave Subaddress byte Data to be written in address specified by subaddress Stop condition Subaddress0 Slave Address A A Data 0 Subaddress1 Description A P A Data 1 A P .....
It is required to input the above-mentioned format from the start condition to the stop condition each time of writing a subaddress For example, when writing the subaddresses 0 to 2, the format should be input three times. In case data of more than one byte are transfered,
S Slave Address A Subaddress0 A Data 0 A P Data n A P
The 4th byte data and following data each are written over the same subaddress. If one of the following matters occurs, the decoder will not return "A" (Acknowledge). * The slave address does not match. * A non-existent subaddress is specified. * The write attribute of a register does not match "X" (write control bit). The input timing is shown below.
SDA SCL
1
2
8
ACK
1
2
8
ACK
1
2
8
ACK
S Start Condition
Slave Address
Slave Address
Data
P Stop Condition
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OPERATION MODE SETTING
The video mode includes ; 1. Internal terminal mode to be directly set by a dedicated terminal 2. Register setting mode to be specified by setting the internal registers These modes can be changed by the mode register MRA [4]. The reset state (default) is the external terminal mode. The following registers can be set in the external terminal mode. MRA[3] input signal mode *0: 1: *000: 001: 010: 100: 101: Composite video input S-video input NTSC ITU-R601 NTSC Square Pixel MTSC 4Fsc PAL ITU-R601 PAL Square Pixel 13.5MHz 12.27MHz 14.32MHz 13.5MHz 14.75MHz
MRA[2 : 0]
input mode
INTERNAL REGISTERS
Register List
Register List Mode Register A (MRA) Mode Register B (MRB) Horizontal Sync Trimer (HSYT) Horizontal Clamp Trimer (HCLT) Horizontal Sync Delay (HSDL) Horizontal Valid Trimer (HVALT) Vertical Valid Trimer (VVALT) Luminance Control (LUMC) AGC Loop filter Control (AGCLF) Sync separation level (SSEPL) Chrominance Control (CHRC) ACC Loop filter Control (ACCCLF) Hue Control (HUE) Output enable Control (OEC) Output Phase Control for Data Y Output Phase Control for Data C Subaddress 0 1 2 3 4 5 6 7 8 9 A B C D E F CHRC7 HUE7 OEC7 OPCY7 OPCC7 Data byte D7 MRA7 MRB7 HSYT7 HCLT7 HSDL7 D6 MRA6 MRB6 HSYT6 HCLT6 HSDL6 D5 MRA5 MRB5 HSYT5 HCLT5 HSDL5 D4 MRA4 MRB4 HSYT4 HCLT4 HSDL4 D3 MRA3 MRB3 HSYT3 HCLT3 HSDL3 D2 MRA2 MRB2 HSYT2 HCLT2 HSDL2 D1 MRA1 MRB1 HSYT1 HCLT1 HSDL1 D0 MRA0 MRB0 HSYT0 HCLT0 HSDL0
HVALT7 HVALT6 HVALT5 HVALT4 HVALT3 HVALT2 HVALT1 HVALT0 VVALT7 VVALT6 VVALT5 VVALT4 VVALT3 VVALT2 VVALT1 VVALT0 LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0 AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0 CHRC6 HUE6 OEC6 OPCY6 OPCC6 CHRC5 HUE5 OEC5 OPCY5 OPCC5 CHRC4 HUE4 OEC4 OPCY4 OPCC4 CHRC3 HUE3 OEC3 OPCY3 OPCC3 CHRC2 HUE2 OEC2 OPCY2 OPCC2 CHRC1 HUE1 OEC1 OPCY1 OPCC1 CHRC0 HUE0 OEC0 OPCY0 OPCC0 ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0
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Register Description
Registers controlled by I2C bus are shown below. A register setting value with an "*" indicates the default. Mode Register A (MRA) MRA[7] MRA[6] Undefined Synchronization mode 0: *1: *0: 1: *0: 1: *0: 1: *000: 001: 010: 100: 101: TV mode VTR mode Offset binary 2's Complement external terminal mode register mode composite video input S video input NTSC CCIR601 NTSC Square Pixel NTSC 4Fsc PAL CCIR601 PAL Square Pixel 13.5MHz 12.27MHz 14.32MHz 13.5MHz 14.75MHz
MRA[5]
Chroma format
MRA[4]
Override
MRA[3]
Video Input mode
MRA[2:0]
Video Input mode
Mode Register B (MRB) MRB[7] Sub Pixel Alignment *0: 1: *0: Sub Pixel Alignment is used. Sub Pixel Alignment is not used. Auto color killer (Chrominance signal level becomes "0" when color burst level is below specified value.) Forced color killer ON (Chrominance signal level is forced to be "0".) (4:2:2) 1: (4:1:1)
MRB[6]
Color killer mode
*1:
MRB[5] MRB[4]
Pixel Sampling Ratio Blue Back
*0: 0: *1:
OFF (Video signal is demodulated and output regardless detection of synchronization.) AUTO (Blue Back is output when synchronization is not detected.)
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MRB[3]
Sync enable, clamping pulse *0: 1: Black level control 0: *1:
HCL, HSY outputs "HIGH" levle HCL, HSY outputs active Black level 7.5IRE Black level 0IRE (Valid only for NTSC input.) adaptive comb filter (Operation mode is selected monitoring the correlation of 3 lines.) nonadaptive comb filter (Operation mode is always fixed.) Comb filter is not used. undefined
MRB[2]
MRB[1:0]
Y/C separation mode
*00:
01:
10: 11:
Horizontal Sync Trimer (HSYT) HSYT[7:4] HSYT[3:0] HSY begin trimer (8/pixel) HSY stop trimer (8/pixel) 0xC: -4 (-32) 0xC: -4 (-32) ~0xB: +11 (+88) ~0xB: +11 (+88)
Horizontal Clamp Trimer (HCLT) HCLT[7:4] HCLT[3:0] HCL begin trimer (8/pixel) HCL stop trimer (8/pixel) 0x8: -8 (-64) 0x8: -8 (-64) ~0x7: +7 (+56) ~0x7: +7 (+56)
Horizontal Sync Delay (HSDL) HSDL[7:4] HSYNC_L delay trimer (4/pixel) 0x80: -128 (-512) ~0x7F: +127 (508)
Horizontal Valid Trimer (HVALT) HVALT[7:4] HVALT[3:0] HVALID begin trimer (1/pixel) HVALID stop trimer (1/pixel) 0x4: -8 (-64) 0x4: -8 (-64) ~0x3: +7 (56) ~0x3: +7 (56)
Vertical Valid Trimer (VVALT) VVALT[7:4] VVALT[3:0] VVALID begin trimer (/line) VVALID stop trimer (/line) 0x8: -8 0x8: -8 ~0x7: +7 ~0x7: +7 23/35
Semiconductor Luminance Control (LUMC) LUMC[7] LUMC[6] Undefined Use of Pre-filter 0: *1: *00: 01: 10: 11: *00: 01: 10: 11: Prefilter is not used. Prefilter is used. middle range
MSM7660
LUMC[5:4]
Aperture bandpass select
high range coring off +/-3LSB +/-4LSB +/-6LSB
LUMC[3:2]
Coring range select
LUMC[1:0]
Aperture filter weighting factor *00: 01: 10: 11:
0 0.25 0.5 1
AGC Loop filter control (AGCLF) AGCLF[7:6] AGC loop filter time constant 00: *01: 10: 11: AGC reference level 0x20:
slow medium fast fixed -32 ~0xIF: +31
AGCLF[5:0]
Sync separation level (SSEPL) SSEPL[6:0] Sync separation level 0x40: -64 ~0x3F: +63
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Semiconductor Chrominance Control (CHRC) CHRC[7:3] CHRC[2] CHRC[1:0] Undefined Chroma bandpass filter Color kill threshold factor 0: 00: *01: 10: 11: OFF *1: ON
MSM7660
0.5*color burst level 0.25*color burst level 0.125*color burst level Undefined
ACC Loop filter control (ACCLF) ACCLF[7] ACCLF[6:5] Undefined ACC loop filter time constant 00: *01: 10: 11: ACC reference level 0x10:
slow medium fast fixed -16 ~0x0F: +15
ACCLF[4:0]
Hue control (HUE) HUE[7:0] Hue control 0x80: -180 degrees ~0x7F: 178.6 degrees
Output enable control (OEC) OEC[7:4] OEC[3] Undefined Output enable for data C 0: *1: Hi-impedance active Hi-impedance active Hi-impedance active Hi-impedance active
OEC[2]
Output enable for HSYNC_L 0: *1: Output enable for VSYNC_L 0: *1: Output enable for data Y 0: *1:
OEC[1]
OEC[0]
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Semiconductor Output phase control for data Y (OPCY) OPCY[7:2] OPCY[1:0] Undefined Output phase control for data Y *0: 1: 2: 3: normal forward l clock Undefined backward l clock
MSM7660
Output phase control for data C (OPCC) OPCCY[7:2] OPCC[1:0] Undefined Output phase control for data C *0: 1: 2: 3: normal forward l clock Undefined backward l clock
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Semiconductor Relationship between Register Setting Value and Adjusted Value Horizontal Sync Timer Position adjustment of sync chip clamp timing signal HSYT [7:4] :Adjusting the starting position
D E F 0 0 1 2 3 4 5 6 7 8 9 A
MSM7660
Register Setting Value (Ox) C
B
Adjusted Value (Pixel) -32 -24 -16 -8
+8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
HSYT [3:0]
:Adjusting the end position
D E F 0 0 1 2 3 4 5 6 7 8 9 A B +8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88
Register Setting Value (Ox) C
Adjusted Value (Pixel) -32 -24 -16 -8
Horizontal Clamp Timer Position adjustment of pedestal clamp timing signal HCLT [7:4]
Register Setting Value (Ox)
:Adjusting the starting position
8 9 A B C D E F 0 0 1 2 3 4 5 6 7 +8 +16 +24 +32 +40 +48 +56
Adjusted Value (Pixel) -64 -56 -48 -40 -32 -24 -16 -8
HCLT [3:0]
Register Setting Value (Ox)
:Adjusting the end position
8 9 A B C D E F 0 0 1 2 3 4 5 6 7 +8 +16 +24 +32 +40 +48 +56
Adjusted Value (Pixel) -64 -56 -48 -40 -32 -24 -16 -8
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Semiconductor Horizontal Sync Delay Adjustment of the starting position of horizontal sync signal HSDL [7:0]
MSB[7 : 4] 8 0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F 9 A B C D E F 0 0 +4 +8 +12 +16 +20 +24 +28 +32 1 2 3 4 5 6
MSM7660
7
-512 -448 -384 -320 -256 -192 -128 -64 -508 -444 -380 -316 -252 -188 -124 -60 -504 -440 -376 -312 -248 -184 -120 -56 -500 -436 -372 -308 -244 -180 -116 -52 -496 -432 -368 -304 -240 -176 -112 -48 -492 -428 -364 -300 -236 -172 -108 -44 -488 -424 -360 -296 -232 -168 -104 -40 -484 -420 -356 -292 -228 -164 -100 -36 -480 -416 -352 v288 -224 -160 -96 -476 -412 -348 -284 -220 -156 -92 -472 -408 -344 -280 -216 -152 -88 -468 -404 -340 -276 -212 -148 -84 -464 -400 -336 -272 -208 -144 -80 -460 -396 -332 -268 -204 -140 -76 -456 -392 -328 -264 -200 -136 -72 -452 -388 -324 -260 -196 -132 -68 -32 -28 -24 -20 -16 -12 -8 -4
+64 +128 +192 +256 +320 +384 +448 +68 +132 +196 +260 +324 +388 +452 +72 +136 +200 +264 +328 +392 +456 +76 +140 +204 +268 +332 +396 +460 +80 +144 +208 +272 +336 +400 +464 +84 +148 +212 +276 +340 +404 +468 +88 +152 +216 +280 +344 +408 +472 +92 +156 +220 +284 +348 +412 +476 +96 +160 +224 +288 +352 +416 +480
+36 +100 +164 +228 +292 +356 +420 +484 +40 +104 +168 +232 +296 +360 +424 +488 +44 +108 +172 +236 +300 +364 +428 +492 +48 +112 +176 +240 +304 +368 +432 +496 +52 +116 +180 +244 +308 +372 +436 +500 +56 +120 +184 +248 +312 +376 +440 +504 +60 +124 +188 +252 +316 +380 +444 +508
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Semiconductor Horizontal Valid Timer Position adjustment of horizontal valid pixel timing signal HVALT [7:4]
Register Setting Value (Ox)
MSM7660
:Adjusting the starting position
8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Pixel) -8
HVALT [3:0]
Register Setting Value (Ox)
:Adjusting the end position
8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Pixel) -8
Vertical Valid Timer Position adjustment of vertical valid line timing signal VVALT [7:4]
Register Setting Value (Ox)
:Adjusting the starting position
8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Line)
VVALT [3:0]
Register Setting Value (Ox)
:Adjusting the end position
8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7
Adjusted Value (Line)
AGC Loop filter control AGCLF [5:0]
Register Setting Value (Ox)
:Adjusting sync level
MSB [5 : 4] 3 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31
2 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
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Semiconductor Sync separation lavel SSEPL [6:0]
Register Setting Value (Ox)
MSM7660
:Adjusting the blanking level
MSB [6 : 4] 4 5 -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 6 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 7 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 2 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 3 +48 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
-64 -63 -62 -61 -60 -59 -58 -57 -56 -55 -54 -53 -52 -51 -50 -49
ACC Loop filter control ACCLF [4:0]
Register Setting Value (Ox)
:Adjusting the color burst level
MSB [4] 1 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
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Semiconductor Hue control Adjustment of color subcarrier phase HUE [7:0]
Register Setting Value (Ox)
MSM7660
MSB [7 : 4] 8 9 A B C
-90.0 -88.6 -87.2 -85.8 -84.4 -83.0 -81.6 -80.2 -78.8 -77.3 -75.9 -74.5 -73.1 -71.7 -70.3 -68.9
D
-67.5 -66.1 -64.7 -63.3 -61.9 -60.5 -59.1 -57.7 -56.3 -54.8 -53.4 -52.0 -50.6 -49.2 -47.8 -46.4
E
-45.0 -43.6 -42.2 -40.8 -39.4 -38.0 -36.6 -35.2 -33.8 -32.3 -30.9 -29.5 -28.1 -26.7 -25.3 -23.9
F
-22.5 -21.1 -19.7 -18.3 -16.9 -15.5 -14.1 -12.7 -11.3 -9.8 -8.4 -7.0 -5.6 -4.2 -2.8 -1.4
0
+0.0 +1.4 +2.8 +4.2 +5.6 +7.0 +8.4 +9.8 +11.3 +12.7 +14.1 +15.5 +16.9 +18.3 +19.7 +21.1
1
+22.5 +23.9 +25.3 +26.7 +28.1 +29.5 +30.9 +32.3 +33.8 +35.2 +36.6 +38.0 +39.4 +40.8 +42.2 +43.6
2
+45.0 +46.4 +47.8 +49.2 +50.6 +52.0 +53.4 +54.8 +56.3 +57.7 +59.1 +60.5 +61.9 +63.3 +64.7 +66.1
3
+67.5 +68.9 +70.3 +71.7 +73.1 +74.5 +75.9 +77.3 +78.8 +80.2 +81.6 +83.0 +84.4 +85.8 +87.2 +88.6
4
+90.0 +91.4 +92.8 +94.2 +95.6 +97.0 +98.4 +99.8
5
6
7
0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F
-180.0 -157.5 -135.0 -112.5 -178.6 -156.1 -133.6 -111.1 -177.2 -154.7 -132.2 -109.7 -175.8 -153.3 -130.8 -108.3 -174.4 -151.9 -129.4 -106.9 -173.0 -150.5 -128.0 -105.5 -171.6 -149.1 -126.6 -104.1 -170.2 -147.7 -125.2 -102.7 -168.8 -146.3 -123.8 -101.3 -167.3 -144.8 -122.3 -165.9 -143.4 -120.9 -164.5 -142.0 -119.5 -163.1 -140.6 -118.1 -161.7. -139.2 -116.7 -160.3 -137.8 -115.3 -158.9 -136.4 -113.9 -99.8 -98.4 -97.0 -95.6 -94.2 -92.8 -91.4
+112.5 +135.0 +157.5 +113.9 +136.4 +158.9 +115.3 +137.8 +160.3 +116.7 +139.2 +161.7 +118.1 +140.6 +163.1 +119.5 +142.0 +164.5 +120.9 +143.4 +165.9 +122.3 +144.8 +167.3
+101.3 +123.8 +146.3 +168.8 +102.7 +125.2 +147.7 +170.2 +104.1 +126.6 +149.1 +171.6 +105.5 +128.0 +150.5 +173.0 +106.9 +129.4 +151.9 +174.4 +108.3 +130.8 +153.3 +175.8 +109.7 +132.2 +154.7 +177.2 +111.1 +133.6 +156.1 +178.6
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Semiconductor
MSM7660
APPLICATION CIRCUIT EXAMPLE
Example of supplying the pixel clock from an external source
5V 5V RI RI 5V 5V 3.3V
I2C Controller
74HCO4
CVBS0...CVBS7 CLKO HCL HSY SCL SDA RESTEL CLKDIV VDD5 COE1 VDD3 Y0...Y7
RCA JACK Composite siganal or luminance signal 470 m 10 m 100 k 75
75
A/D C Sony CXD 1176Q
MSM7660
AGND RCA JACK Chrominance signal 470 m 10 m 100 k 75 AGND CLKX2 CLKX2O CSYNC-L HSYNC-L VSYNC-L 75
A/D C Sony CXD 1176Q
OE-L MODE3 MODE2 MODE1 MODE0
Dip SW
GND
X
ODD VVALID HVALID C0...C7
32/35
Frame memory or image LSI
CD0...CD7
Semiconductor
MSM7660
CASCADE PRIORITY CONTROL
The MSM7660 can set Y/C signal output to high impedance, and can be wired with another bus that can be set to high impedance output. Y/C output enable/disable is selected by the OE_L pin and register OEC. Cascade connection of COEI and COEO makes priority control possible. Priority is assigned to devices and when a device with higher priority is in enable status, devices with lower priority are automatically disabled. The priority control table is shown below.
Register setting
OEC[0] OEC[1] OEC[2] OEC[3]
Input coei 0 1 1 1 1 1 1 ce_l X 1 1 1 1 1 0 X 0 1 0 1 0 X Z Z enable enable Z Z enable Z Z Z Z Z enable enable
Output Y0..Y7 VSYNC_l HSYNC_l C0..C7 Z Z Z Z Z enable enable Z Z enable Z enable Z enable COEO 0 1 0 0 0 1 0
X 0 1 1 0 0 X
X 0 0 0 0 1 X
X 0 0 0 0 1 X
Z : High impedance
Cascade Priority Control Table
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Semiconductor
MSM7660
COEI CVBS7..0#1 CD7..0#1 oe_l#1 Y0..Y7 MSM7660 DECODER#1 HVALD VVALD OE_L COEO CDD C0..C7 Frame memory Frame memory Controler
COEI CVBS7..0#2 CD7..0#2 oe_l#2 Y0..Y7 C0..C7 MSM7660 DECODER#2 HVALD VVALD OE_L COEO CDD
COEI CVBS7..0#n CD7..0#n oe_l#n Y0..Y7 C0..C7 MSM7660 HVALD DECODER#n VVALD OE_L COEO CDD
Cascade Priority Control Connection Example
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Semiconductor
MSM7660
PACKAGE OUTLINES AND DIMENSIONS
25.00.2 20.00.2 ^4 $1 $0 ^5
19.00.2
14.00.2
*0
q INDEX MARK Mirror finished surface 0.8TYP.
0.170.05
0.05 to 0.35
0.25
0.8 0.12 2.5TYP.
@5 @4 0.32
+0.08 -0.07
0.16
M
SEATING PLANE
2.5MAX.
2.10.2
0 to 10
1.3TYP. 1.380.15
1.0TYP.
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